Home / ubuntu / Questions / 1226433
In Process
opinion_no9
Asked: 2020-04-13 01:16:54 +0800 CST

[drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00 spams my dmesg

  • 772

dmesg messages are spamed with gazillions of entries like:

[drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
[drm:intel_power_well_enable [i915]] enabling DC off

and then back 

[drm:skl_enable_dc6 [i915]] Enabling DC6
[drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02

on my laptop having Intel i915 GPU and Ubuntu latest.

Some messages per fraction of a second. dmesg is unusable this way. I want to stop that.

What I found: The built in Intel i915 graphics can be controlled by Kernel parameters like i915.disable_power_well.

Intel explains:

disable_power_well:Disable display power wells when possible (-1=auto [default], 0=power wells always on, 1=power wells disabled when possible) (int)

My problem: As a non native speaker I do not get the gist of "display power wells". Can someone please tell me the meaning of Intel "power wells"?

I intend to change this unacceptable behaviour by using kernel parameter 

i915.disable_power_well= ....

What value is most appropriate?

kernel i915 intel-graphics

1 Answers

  1. I also have the same 'gazillions of entries' in my logs but I made them appear on purpose with kernel option drm.debug=0xe so they are debug messages that should not appear in your log by default. So I suppose that a simple drm.debug=0x0 should remove the annoying 'gazillions of entries' or you have something else that force these messages to appear.

    You can print information about kernel parameter sudo modinfo -p drm especially about the debug parameter:

    debug:Enable debug output, where each bit enables a debug category.
        Bit 0 (0x01)  will enable CORE messages (drm core code)
        Bit 1 (0x02)  will enable DRIVER messages (drm controller code)
        Bit 2 (0x04)  will enable KMS messages (modesetting code)
        Bit 3 (0x08)  will enable PRIME messages (prime code)
        Bit 4 (0x10)  will enable ATOMIC messages (atomic code)
        Bit 5 (0x20)  will enable VBL messages (vblank code)
        Bit 7 (0x80)  will enable LEASE messages (leasing code)
        Bit 8 (0x100) will enable DP messages (displayport code) (int)

    Now I have no idea if power_well could solve your problem you can try each value 0 and 1 and see what happens but I think these messages are more related to i915.enable_dc.

    • 1